P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0)

Table 133.  ATS Enhanced Capability Header
Bits Register Description Default Value Access
[15:0] PCI Express Extended Capability ID 0x000F RO
[19:16] Capability Version 0x1 RO
[31:20] Next Capability Pointer: Points to Null

See description.

Programmed via Programming Interface.

RO