P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)

This register provides a user configurable device or board ID so that the user software can determine which .sof file to load into the device.

This register is only available for Port 0 ( PCIe* Gen4 x16). It is blocked for the other Ports.

Table 144.  User Configurable Device and Board ID Register
Bits Register Description Default Value Access
[15:0] This register allows you to specify the ID of the .sof file to be loaded.

From configuration bits

RO