Derating method. The default settings are based on Intel internal board simulation data. To obtain accurate timing analysis according to the condition of your board, Intel recommends that you perform board simulation and enter the slew rate in the Intel® Quartus® Prime software to calculate the derated setup and hold time automatically or enter the derated setup and hold time directly.

CK/CK# slew rate (differential).

Address and command slew rate.

DQS and DQS# slew rate (differential).

DQ slew rate.

Address/command setup time to CK.

Address/command hold time from CK.

Data setup time to DQS.

Data hold time from DQS.

Choose between default Intel settings (with specific Intel boards) or manually enter board simulation numbers obtained for your specific board.

The reduction in the eye diagram on the setup side (or left side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI. (For single rank designs, ISI can be zero; in multirank designs, ISI is necessary for accurate timing analysis.)

The reduction in the eye diagram on the hold side (or right side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI.

The total reduction in the eye diagram due to ISI on DQ signals compared to a case when there is no ISI. Intel assumes that the ISI reduces the eye width symmetrically on the left and right side of the eye.

The increase in variation on the range of arrival times of DQS compared to a case when there is no ISI. Intel assumes that the ISI causes DQS to further vary symmetrically to the left and to the right.

The delay of the longest CK trace from the FPGA to the memory device is expressed by the following equation:

Where n is the number of memory clock and r is number rank of device.

The delay of the longest DQS trace from the FPGA to the memory device, whether on a DIMM or the same PCB as the FPGA is expressed by the following equation:

Where n is the number of DQS and r is number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQS delay is expressed by the following equation:

The minimum skew or smallest positive skew (or largest negative skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all DIMMs/devices is expressed by the following equation:

Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the minimum delay difference between CK and DQS is expressed by the following equation:

This parameter value affects the write leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to non-leveling configurations of any number of ranks with the requirement that DQS must have positive margins in Timequest Report DDR.

For multiple boards, the minimum skew between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:

The maximum skew or smallest negative skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all DIMMs/devices is expressed by the following equation:

Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the maximum delay difference between CK and DQS is expressed by the following equation:

This value affects the write Leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to non-leveling configurations of any number of ranks with the requirement that DQS must have positive margins in Timequest Report DDR.

For multiple boards, the maximum skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:

The largest skew among DQ and DM signals in a DQS group. This value affects the read capture and write margins for DDR2 and DDR3 SDRAM interfaces in all configurations (single or multiple chip-select, DIMM or component).

For multiple boards, the largest skew between DQ and DM signals in a DQS group is expressed by the following equation:

The largest skew between DQS signals in different DQS groups. This value affects the resynchronization margin in memory interfaces without leveling such as DDR2 SDRAM and discrete-device DDR3 SDRAM in both single- or multiple chip-select configurations.

For multiple boards, the largest skew between DQS signals in different DQS groups is expressed by the following equation, if you want to use the same design for several different boards:

The average delay difference between each DQ signal and the DQS signal, calculated by averaging the longest and smallest DQ signal delay values minus the delay of DQS. The average delay difference between DQ and DQS is expressed by the following equation:

where n is the number of DQS groups. For multi-rank or multiple CS configuration, the equation is:

The largest skew between the address and command signals for a single board is expressed by the following equation:

For multiple boards, the largest skew between the address and command signals is expressed by the following equation, if you want to use the same design for several different boards:

A value equal to the average of the longest and smallest address and command signal delay values, minus the delay of the CK signal. The value can be positive or negative. Positive values represent address and command signals that are longer than CK signals; negative values represent address and command signals that are shorter than CK signals. The average delay difference between address and command and CK is expressed by the following equation:

where n is the number of memory clocks. For multi-rank or multiple CS configuration, the equation is:

The Intel® Quartus® Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins for DDR2 and DDR3 SDRAM interfaces. You should derive this value through board simulation.

For multiple boards, the average delay difference between address and command and CK is expressed by the following equation, if you want to use the same design for several different boards: