Intel® MAX® 10 External Memory Interface User Guide

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ID 683087
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 External Memory Interface Overview 2. Intel® MAX® 10 External Memory Interface Architecture and Features 3. Intel® MAX® 10 External Memory Interface Design Considerations 4. Intel® MAX® 10 External Memory Interface Implementation Guides 5. UniPHY IP References for Intel® MAX® 10 Devices 6. Intel® MAX® 10 External Memory Interface User Guide Archives 7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
1. Intel® MAX® 10 External Memory Interface Overview x
1.1. Intel® MAX® 10 External Memory Interface Support and Performance
2. Intel® MAX® 10 External Memory Interface Architecture and Features x
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface 2.2. Intel® MAX® 10 DQ/DQS Groups 2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width 2.4. Intel® MAX® 10 Memory Controller 2.5. Intel® MAX® 10 External Memory Read Datapath 2.6. Intel® MAX® 10 External Memory Write Datapath 2.7. Intel® MAX® 10 Address/Command Path 2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network 2.9. Phase Detector for VT Tracking 2.10. On-Chip Termination 2.11. Phase-Locked Loop 2.12. Intel® MAX® 10 Low Power Feature
2.5. Intel® MAX® 10 External Memory Read Datapath x
2.5.1. DDR Input Registers
2.6. Intel® MAX® 10 External Memory Write Datapath x
2.6.1. DDR Output Registers
3. Intel® MAX® 10 External Memory Interface Design Considerations x
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations 3.2. LPDDR2 Design Considerations 3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation 3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations x
3.1.1. DDR2/DDR3 External Memory Interface Pins 3.1.2. DDR2/DDR3 Recommended Termination Schemes for Intel® MAX® 10 Devices
3.1.1. DDR2/DDR3 External Memory Interface Pins x
3.1.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins 3.1.1.2. Data Mask Pins 3.1.1.3. DDR2/DDR3 Error Correction Coding Pins 3.1.1.4. DDR2/DDR3 Address and Control/Command Pins 3.1.1.5. Memory Clock Pins
3.1.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.1.1.1.1. Intel® MAX® 10 I/O Bank DQ/DQS Support for DDR2/DDR3
3.2. LPDDR2 Design Considerations x
3.2.1. LPDDR2 External Memory Interface Pins 3.2.2. LPPDDR2 Power Supply Variation Constraint 3.2.3. LPDDR2 Recommended Termination Schemes for Intel® MAX® 10 Devices
3.2.1. LPDDR2 External Memory Interface Pins x
3.2.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins 3.2.1.2. Data Mask Pins 3.2.1.3. LPDDR2 Address and Control/Command Pins 3.2.1.4. Memory Clock Pins
3.2.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.2.1.1.1. Intel® MAX® 10 I/O Bank DQ/DQS Support for LPDDR2
4. Intel® MAX® 10 External Memory Interface Implementation Guides x
4.1. UniPHY IP Core 4.2. LPDDR2 External Memory Interface Implementation 4.3. DDR2 and DDR3 External Memory Interface Implementation
4.2. LPDDR2 External Memory Interface Implementation x
4.2.1. Supported LPDDR2 Topology
4.3. DDR2 and DDR3 External Memory Interface Implementation x
4.3.1. Intel® MAX® 10 Supported DDR2 or DDR3 Topology
5. UniPHY IP References for Intel® MAX® 10 Devices x
5.1. UniPHY Parameter Settings for Intel® MAX® 10
5.1. UniPHY Parameter Settings for Intel® MAX® 10 x
5.1.1. UniPHY Parameters—PHY Settings 5.1.2. UniPHY Parameters—Memory Parameters 5.1.3. UniPHY Parameters—Memory Timing 5.1.4. UniPHY Parameters—Board Settings 5.1.5. UniPHY Parameters—Controller Settings 5.1.6. UniPHY Parameters—Diagnostics
1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide

5.1.3. UniPHY Parameters—Memory Timing

Use the Memory Timing options to apply the memory timings from your memory manufacturer’s data sheet.
Table 17.  Memory TimingFor each parameter, refer to the memory vendor data sheet.
Parameter Applies To Description Set According To
tIS (base) DDR2, DDR3, LPDDR2

Address and control setup to CK clock rise.

 Memory speed grade
tIH (base) DDR2, DDR3, LPDDR2

Address and control hold after CK clock rise.

Memory speed grade
tDS (base) DDR2, DDR3, LPDDR2

Data setup to clock (DQS) rise.

Memory speed grade
tDH (base) DDR2, DDR3, LPDDR2

Data hold after clock (DQS) rise.

Memory speed grade
tDQSQ DDR2, DDR3, LPDDR2

DQS, DQS# to DQ skew, per access.

Memory speed grade
tQHS DDR2, LPDDR2

DQ output hold time from DQS, DQS# (absolute time value).

Memory speed grade
tQH DDR3

DQ output hold time from DQS, DQS# (percentage of tCK).

Memory speed grade
tDQSCK DDR2, DDR3

DQS output access time from CK/CK#.

 Memory speed grade
tDQSCK (max) LPDDR2
tDQSCK Delta Short LPDDR2

Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160 ns rolling window.

Memory speed grade
tDQSCK Delta Medium LPDDR2

Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 1.6 µs rolling window.

Memory speed grade
tDQSCK Delta Long LPDDR2

Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 32ms rolling window.

Memory speed grade
tDQSS DDR2, DDR3, LPDDR2

First latching edge of DQS to associated clock edge (percentage of tCK).

Memory speed grade
tDQSH DDR2, LPDDR2

DQS Differential High Pulse Width (percentage of tCK). Specifies the minimum high time of the DQS signal received by the memory.

Memory speed grade
tQSH DDR3
tDSH DDR2, DDR3, LPDDR2

DQS falling edge hold time from CK (percentage of tCK).

Memory speed grade
tDSS DDR2, DDR3, LPDDR2

DQS falling edge to CK setup time (percentage of tCK).

Memory speed grade
tINIT DDR2, DDR3, LPDDR2

Memory initialization time at power-up.

 Memory speed grade
tMRD DDR2, DDR3

Load mode register command period.

Memory speed grade
tMRW LPDDR2
tRAS DDR2, DDR3, LPDDR2

Active to precharge time.

 Memory speed grade
tRCD DDR2, DDR3, LPDDR2

Active to read or write time.

 Memory speed grade
tRP DDR2, DDR3, LPDDR2

Precharge command period.

 Memory speed grade
tREFI DDR2, DDR3

Refresh command interval.

 Memory speed grade and temperature range
tREFIab LPDDR2

Refresh command interval (all banks).

 Memory speed grade
tRFC DDR2, DDR3

Auto-refresh command interval.

 Memory device capacity
tRFCab LPDDR2

Auto-refresh command interval (all banks).

 Memory device capacity
tWR DDR2, DDR3, LPDDR2

Write recovery time.

 Memory speed grade
tWTR DDR2, DDR3, LPDDR2

Write to read period.

Calculate the value based on the memory clock frequency.

Memory speed grade and memory clock frequency
tFAW DDR2, DDR3, LPDDR2

Four active window time.

 Memory speed grade and page size
tRRD DDR2, DDR3, LPDDR2

RAS to RAS delay time.

Calculate the value based on the memory clock frequency.

Memory speed grade, page size and memory clock frequency
tRTP DDR2, DDR3, LPDDR2

Read to precharge time.

Calculate the value based on the memory clock frequency.

Memory speed grade and memory clock frequency
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