Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Public
Document Table of Contents

3.1. Copying the Configuration Space Bypass Mode Example Design

Follow these steps to copy the Configuration Space Bypass Mode Qsys Example Design to your working directory: altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g2x8_ast256.qsys

  1. Copy the example design, pcie_cfbp_g2x8_ast256.qsys, from the installation directory <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/ to your working directory.
  2. Copy the Qsys wrapper file for the Configuration Space Bypass application logic, altera_pcie_cfgbp_ed_hw.tcl, from the installation directory <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/ to your working directory.
  3. Rename the pcie_cfbp_g2x8_ast256.qsys top.qys. Renaming is necessary because the testbench defines top.v as the top-level wrapper. Qsys creates top.v from top.qsys when you generate the system.
  4. Start Qsys by typing qsys-edit and open top.qsys when prompted by Qsys.

The following figure shows the complete system.

Figure 10. Configuration Bypass Qsys System
  1. Note the following parameter settings for the Configuration Space Bypass Example Design:
  • For the DUT, the Enable Configuration Bypass parameter is turned on under the System Settings banner.
  • The Base Address Registers specify BAR0 as 1 MByte - 20 bits of 64-bit prefetchable memory for each function. In Configuration Space Bypass Mode, the BAR registers inside the Hard IP for PCI Express are not used. The Application Layer implements the Configuration Space for each function.
  • For testbench compatibility, the Config-Bypass App Example, labeled APPs, must retain a Device ID of 0xE001 (5734510) and a Vendor ID of 0x1172 (446610).