Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Public
Document Table of Contents

3.3. Simulating the Example Design

Follow these steps to simulate the Qsys system using ModelSim:

  1. In a terminal window, change to the <working_dir>/top/testbench/mentor directory.
  2. Start the ModelSim simulator by typing vsim.
  3. To compile the simulation, type the following commands in the terminal window:
  • source msim_setup.tcl (The msim_setup.tcl file defines aliases.
  • ld_debug (The ld_debug command argument stops optimizations, improving visibility in the ModelSim waveforms. )

The following figure shows the design hierarchy for the Configuration Space Bypass Example Design after compilation.

Figure 11.  Design Hierarchy for the Configuration Space Bypass Example Design for 256-Bit Avalon-ST Interface
  1. To observe the simulation, on the ModelSim View menu, select wave. Then add some key interfaces to the wave window. The following four interfaces under the /top_tb/top_inst/apps/altpcierd_cfbp_top/cfgbp_app_ctrl/genblk1 illustrate the TX and RX interfaces, the current state, and configuration.
    • *RxSt*
    • *TxSt*
    • *Rxm*
    • *_state*
    • cfg_*
  2. To run the simulation, type the following command: run -all
Note: By default, the simulation is serial, to simulate using the parallel PIPE interface, you can change the default value of the serial_sim_hwtcl parameter from 1 to 0 in altera_pcie_cfgbp_ed/top/testbench/top_tb/simulation/top_tb.v. After changing that value, you must recompile the simulation to pick up the new value of the serial_sim_hwtcl parameter before running the simulation.