AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

Download PDF
ID 683191
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines x
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core 1.2. Migration Flow 1.3. AN 735 Document Revision History
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core x
1.1.1. Architecture Overview 1.1.2. Clock and Reset Scheme 1.1.3. Interface Signals
1.2. Migration Flow x
1.2.1. Instantiating Low Latency Ethernet MAC IP Core 1.2.2. Generating 156.25 MHz and 312.5 MHz Clock 1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

1.1.1. Architecture Overview

To support seamless migration from 10GbE MAC IP core to Low Latency Ethernet 10G MAC IP core, there are three additional modules in the design.

These three modules are:

  • 64-bit Avalon-ST adapter for both TX and RX datapaths
  • 64-bit Avalon-MM adapter
  • 64-bit XGMII adapter for both TX and RX datapaths

The Avalon-ST adapter converts 32-bit datapath from the MAC to 64-bit datapath to the user interface while the Avalon-MM adapter converts the register mapping of the Low Latency Ethernet 10G MAC IP core to the 10GbE MAC IP core register mapping. This register mapping conversion enables existing users of the 10GbE MAC IP core to migrate to the Low Latency Ethernet 10G MAC IP core without any software modification.

Figure 1.  Multispeed 10M/100M/1G/10GbE 10GbE MAC IP Core Block Diagram


Figure 2.  Multispeed 10M/100M/1G/10GbE Low Latency Ethernet 10G MAC IP Core Block Diagram


Level Two Title