4. I/O Voltage Support in the JTAG Chain
A JTAG chain can contain several Intel FPGA and non-Intel FPGA devices.
The TDO pin of a device drives out at the voltage level according to the VCCIO of the device. The devices can interface with each other although the devices may have different VCCIO levels.
For example, a device with 3.3-V VCCIO can drive to a device with 5.0-V VCCIO because 3.3 V meets the minimum VIH on transistor-to-transistor logic (TTL)-level input for the 5.0-V VCCIO device.
Intel® MAX® 10 devices can support 1.5-, 1.8-, 2.5-, or 3.3-V input levels, depending on the VCCIO voltage of I/O Bank 1B.
To interface the TDI and TDO lines of the JTAG pins of devices that have different VCCIO levels, insert a level shifter between the devices. If possible, construct the JTAG chain where device with a higher VCCIO level drives to a device with an equal or lower VCCIO level. In this setup, you only require a level shifter for shifting the TDO level to a level JTAG tester accept.
Figure 3. JTAG Chain of Mixed Voltages and Level Shifters