AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

Download PDF
ID 683231
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines x
1.1. Implementing the Altera PHYLite Design 1.2. Mapping the Interface Signals 1.3. Performance Comparison 1.4. Use Case Examples 1.5. Altera GPIO to Altera PHYLite Design Example 1.6. Document Revision History
1.1. Implementing the Altera PHYLite Design x
1.1.1. Parameter Settings
1.4. Use Case Examples x
1.4.1. Use Case 1: Source Synchronous I/O Interface 1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device 1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces 1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard 1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.5. Altera GPIO to Altera PHYLite Design Example x
1.5.1. Simulation Diagrams 1.5.2. Design Verification
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

1.3. Performance Comparison

The performance comparison between the Altera GPIO and Altera PHYLite for Parallel Interfaces IP cores measures the setup and hold timing slack window at 200 Mbps.
The comparison between Altera GPIO and Altera PHYLite for Parallel Interfaces IP cores are based on the preliminary timing model in the Quartus Prime software version 15.1, using Arria 10 device (10AX115S2F45I2SGE2). The analysis is done using a simplified design with no user logic in the IP cores.
Note: The timing slack in the following tables do not account for any setup or hold requirements at the receiver or any channel skew between clock and data.
Table 4.  Timing Analysis for Source Synchronous I/O Using GPIO Path
Input/Output SDR/DDR Architecture Clock Network Worst Setup Slack Worst Hold Slack Slack Window (Setup + Hold)1
GPIO Input DDR
  • Data on 0°
  • Clock on 90° (center-aligned)
 Global Clock 1.093 1.177 2.270
Regional Clock 1.149 1.235 2.384
Periphery Clock 1.360 1.415 2.775
SDR
  • Data on 0°
  • Clock on 180° (center-aligned)
 Global Clock 1.188 1.227 2.415
Regional Clock 1.214 1.223 2.452
Periphery Clock 1.409 1.404 2.462
GPIO Output DDR
  • Data on 0°
  • Clock on 90° (center-aligned)
 Global Clock 0.023 1.831 1.854
Regional Clock 0.129 1.844 1.973
Periphery Clock 0.193 1.968 2.161
SDR
  • Data on 0°
  • Clock on 180° (center-aligned)
 Global Clock 0.835 1.541 2.376
Regional Clock 0.408 1.738 2.146
Periphery Clock 0.668 1.842 2.186
Table 5.  Timing Analysis for Source Synchronous I/O Using Altera PHYLite IP Core
Input/Output SDR/DDR Architecture Clock Network Worst Setup Slack Worst Hold Slack Slack Window (Setup + Hold)
Input (1-bit Input) DDR
  • Data on 0°
  • Strobe on 90° (center-aligned)
 PHY clock 2.054 1.995 4.049
SDR
  • Data on 0°
  • Strobe on 180° (center-aligned)
 2.064 2.020 4.084
Output (1-bit Input) DDR
  • Data on 0°
  • Strobe on 90° (center-aligned)
 2.197 2.216 4.413
SDR
  • Data on 0°
  • Strobe on 180° (center-aligned)
 2.239 2.209 4.448

In summary, the timing analysis on the source synchronous I/O implementation on the PHYLite IP core provides much larger timing slack window compared to the GPIO IP core. The PHYLite IP core uses the PHY clock network instead of the global clock networks in the core. The change in the clock network enables the PHYLite IP core to achieve better timing performance and avoid core noise effect.

1 Based from multi corner timing analysis.
Level Two Title