DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Public
Document Table of Contents

11.7.5. DPRX0_AUD_AIF2

Received audio InfoFrame register, DPRX0_AUD_AIF2.

Address: 0×0034

Direction: RO

Reset: 0×00000000

Table 189.  DPRX0_AUD_AIF2 Bits

Bit

Bit Name

Function

31:8

Unused

7:0

AIF

Received audio InfoFrame byte 2 (refer to CEA-861-E specification)