Intel® Stratix® 10 GX Device Errata

ID 683376
Date 1/14/2022
Public

PCI Express Tile Usage Restrictions

Description

If any transceiver channels share a tile with active PCI Express interfaces that are Gen2 or Gen3 capable and bonded with more than two lanes (x4, x8, x16), the maximum data rate supported for the non-PCIe channels in those tiles is 6.5 Gbps. This restriction applies to both Hard IP and Soft IP implementations for the active PCI Express interfaces.

Running the neighboring transceiver channels within the same tile at data rates faster than 6.5 Gbps may result in bit errors being observed during a PCIe speed change. Transceiver channels that share a tile with active PCI Express interfaces that are only Gen1 capable are not impacted.

Workaround

  • Avoid placing other transceiver instances above 6.5 Gbps data rates in the same tile as PCIe channels that are Gen2 or Gen3 capable.
  • Bring up the PCIe channels first, followed by non-PCIe channels.

Status

Affects:

  • Intel® Stratix® 10 GX L-Tile devices (in PIPE mode)

Status: Fixed in:

  • Intel® Stratix® 10 GX L-Tile devices (in Hard IP mode)