Intel® Stratix® 10 GX Device Errata

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ID 683376
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX Device Errata Intel® Stratix® 10 GX Device Errata Revision History
Intel® Stratix® 10 GX Device Errata x
Device Errata for the Intel® Stratix® 10 GX L-Tile Devices Device Errata for the Intel® Stratix® 10 GX H-Tile Devices
Device Errata for the Intel® Stratix® 10 GX L-Tile Devices x
Device Power Supply, Core, Configuration and I/O Transceivers
Device Power Supply, Core, Configuration and I/O x
Power-on Configuration Intermittent Configuration Failures Description Workaround Status Device Security Features Unexpected AVST_READY Signal Behavior After Power-On-Reset (POR) M20K Simple Quad-Port Mode Support
Transceivers x
On-Die Instrumentation (ODI) Support PCI Express Tile Usage Restrictions
Device Errata for the Intel® Stratix® 10 GX H-Tile Devices x
Device Power Supply, Core, Configuration and I/O
Device Power Supply, Core, Configuration and I/O x
M20K Simple Quad-Port Mode Support
Intel® Stratix® 10 GX Device Errata
Intel® Stratix® 10 GX Device Errata Revision History

Power-on Configuration Intermittent Configuration Failures

Description

Your device may encounter intermittent configuration failures if it is not programmed with at least 256 kB of configuration data within 18 seconds after completion of the power up sequence. This erratum does not apply to FPGA reconfiguration, provided a successful configuration was completed after the power up sequence. If the nSTATUS pin remains low for 110 ms after toggling the nCONFIG pin from low to high, it may indicate you have encountered this issue. To confirm, toggle nCONFIG again and if the nSTATUS pin remains low for another 10 ms, then you have confirmed the failure.
Note: Configuration via Protocol (CvP) that uses an open or closed PCIe system must also adhere to the above requirements for successful configuration.

Workaround

Hardware workaround: Use a MOSFET as a switch to briefly toggle the VCCIO_SDM voltage level when the host is ready to configure the FPGA using an arrangement as shown in the figure below.
Figure 1. Hardware Workaround

Software workaround: Configure your FPGA with a dummy design within 18 seconds of the power up sequence completion. When the system is ready to configure, then reconfigure with the full design. Note the following considerations regarding the software workaround:

  • For Intel® Quartus® Prime Pro Edition versions prior to 18.0:
    • You must use the same version of Intel® Quartus® Prime Pro Edition to create the first programmed bitstream and any subsequent programmed bitstreams.
  • For Intel® Quartus® Prime Pro Edition version 18.0:
  • For Intel® Quartus® Prime Pro Edition versions after 18.0:
    • You can create subsequent configuration files with any Intel® Quartus® Prime Pro Edition version later than 18.0.

Status

Affects:
  • Intel® Stratix® 10 GX 2800 L-Tile devices
  • Intel® Stratix® 10 GX 2500 L-Tile devices

Status: If you are using an Intel® Stratix® 10 GX 2800 or 2500 L-Tile device and a fix is required, move to the Intel® Stratix® 10 SX 2800/2500 L-Tile device, which is drop-in compatible.

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