AN 699: Using the Altera Ethernet Design Toolkit

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ID 683469
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Using the Altera Ethernet Design Toolkit
1. Using the Altera Ethernet Design Toolkit x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Getting Started 1.4. AN 699 Document Revision History
1.3. Getting Started x
1.3.1. Configuring the FPGA and Clock 1.3.2. Launching the Ethernet Design Toolkit 1.3.3. Recommended Flow for Using the Ethernet Design Toolkit
1.3.3. Recommended Flow for Using the Ethernet Design Toolkit x
1.3.3.1. Ethernet Design Toolkit Tabs and Settings
1.3.3.1. Ethernet Design Toolkit Tabs and Settings x
1.3.3.1.1. IP Configuration Tab 1.3.3.1.2. IP Status Tab 1.3.3.1.3. Traffic Controller Tab
1. Using the Altera Ethernet Design Toolkit

1.3.1. Configuring the FPGA and Clock

  1. Launch the Quartus II software.
  2. Select Tools > Programmer to configure the FPGA with the generated SOF (.sof) file.

    The zip file includes a .sof file with a two-channel design:

    • Channel 0 : TX/RX serial signal assigned for board trace serial loopback.
    • Channel 1 : TX/RX serial signal assigned to SFP port.
  3. Open the Clock Control tool (ClockControl.exe) from development kit's board test system folder . The Clock Control tool is shipped with the “Installation Kit” of the development board.
  4. Set the target frequency for Y5 to 644.53125 MHz for 10G reference clock source and Y6 to 125 MHz for 1G reference clock source.
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