LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683520
Date 9/20/2022
Public
Document Table of Contents

Setting the Transmitter Output Clock Parameters

You can specify the relationship of tx_outclock to the tx_out data using these parameters:

  • Desired tx_outclock phase shift (degrees)
  • Tx_outclock division factor

The parameters set the phase and frequency of the tx_outclock based on the fast_clock, which operates at the serial data rate. You can specify the desired tx_outclock phase shift relative to the tx_out data at 45° increments of the fast_clock. You can set the tx_outclock frequency using the available division factors from the drop-down list.

Edge-Aligned tx_outclock to tx_out

For rising tx_outclock edge-aligned to the MSB of the serial data on tx_out, specify 0° phase shift.

Figure 7.  0° Edge Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8


Center-Aligned tx_outclock to tx_out

To specify center-aligned relationship between tx_outclock and the MSB of the serial data on tx_out, specify 180° phase shift.

Figure 8.  180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8


  • Phase shift values from 0° to 315° position the rising edge of tx_outclock within the MSB of the tx_out data.
  • Phase shift values starting from 360° position the rising edge of tx_outclock in serial bits after the MSB. For example, a phase shift of 540° positions the rising edge in the center of the bit after the MSB.
Figure 9.  540° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8


Use the Tx_outclock division factor drop-down list to set the tx_outclock frequency.

Figure 10.  180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 2This figure shows a x8 serialization factor using a 180° phase shift with a tx_outclock division factor of 2 (DDR clock and data relationship).