LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 9/20/2022
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Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES Intel® FPGA IP Transmitter Settings

The parameter options in the Transmitter Settings tab are available if you select the TX functional mode in the General Settings tab.
Table 15.  Transmitter Settings Tab
Parameter Value Description
TX core registers clock
  • tx_coreclock
  • inclock

Selects the clock that clocks the core registers:

  • tx_coreclock—selects the tx_coreclock as the clock source.
  • inclock—select the PLL refclk as the clock source. The refclk frequency must be equal to the data rate divided by the serialization factor.

This parameter is available only in the TX functional mode.

Enable tx_coreclock port
  • On
  • Off

Turn on to expose the tx_coreclock port that you can use to drive the core logic feeding the transmitter.

The tx_coreclock signal is a feedthrough of the ext_coreclock input.

Intel recommends that you use the tx_coreclock output signal if it is requested.

Note: This option is disabled if the Use external PLL option in the PLL Settings tab is turned on. To expose the tx_coreclock when using external PLL, turn off Use external PLL option before turning on the Enable tx_coreclock port. After making changes to Enable tx_coreclock port, you can turn Use external PLL back on.
Enable tx_outclock port
  • On
  • Off

Turn on to expose the tx_outclock port.

  • The tx_outclock port frequency depends on the setting for the Tx_outclock division factor parameter.
  • The phases of the tx_outclock_p and tx_outclock_n ports depend on the Desired tx_outclock phase shift parameter.

Turning on this parameter reduces the maximum number of channels per transmitter interface by one channel.
Desired tx_outclock phase shift (degrees)

Refer to related information.

Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock.

Actual tx_outclock phase shift (degrees)

Depends on fast_clock and tx_outclock frequencies. Refer to related information.

Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift.

Tx_outclock division factor Depends on the SERDES factor. Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle.

Section Content
Setting the Transmitter Output Clock Parameters

Related Information
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