PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 9/01/2021
Public

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Document Table of Contents

2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP consists of the following ports:

  • Clocks and reset
  • Core data and control (broken down into input and output paths)
  • I/O (broken down into input and output paths)
Figure 8. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP interface.