AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

About the Functional Safety Separation Flow

This flow extends the widely-adopted, proven Intel® Quartus® Prime incremental compilation flow, which reduces compilation times by up to 70% through logic preservation.

The incremental compilation flow maps the design hierarchy to design partitions that the Intel® Quartus® Prime software treats separately during compilation. Intel defines a design partition as a logical partition. You use logical partitions with a physical placement constraint, a LogicLock region, to form the foundation for the safety flow.

In the functional safety separation flow, you categorize design partitions as either safety IP, which require complete preservation, or nonsafety IP. To configure a safety IP partition, set the partitions Strict preservation setting to On.

When you declare a design partition, every hierarchy within that partition becomes part of the same partition. When you create new partitions for hierarchies within an existing partition, the logic within the new lower-level partition is no longer part of the higher-level partition.

Figure 1. Partitions in a Design Hierarchy B and F-G are design partitions. Partition B includes entity B which contains sub-entities D and E. Partition F-G includes entities F and G. The default partition, top, contains entities A and C which are not assigned to any other partition.


Figure 2. LogicLock Regions for Partitions in a Design Hierarchy

Use a LogicLock region to create a physical placement constraint for the logical partition B.



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