AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
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Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Design Modification Flow

This flow describes the necessary steps for you to modify the nonsafety IP in your design. This flow ensures that the previously compiled safety IP that the project uses remains unchanged when you change or compile nonsafety IP.
CAUTION:
Use the design modification flow only after you qualify your design in the design creation flow.

For a general description of the global assignments required to enable this flow refer to the Intel® Quartus® PrimeSoftware Handbook.

Figure 5. Design Modification Flow


Note: The hash uses the MD5 algorithm.
Note: If your safety IP is a sub-block in a Qsys system, every time you regenerate HDL for the Qsys system, the timestamp for the safety IP HDL changes. When you change any HDL source file that belongs to a safety IP partition, by default the Intel® Quartus® Prime software resynthesises the partition and performs a clean place and route for that partition. For a clean place and route, the design creation flow is active for the safety IP. To change the default so that HDL changes do not cause resynthesis, and to keep the design modification flow active, you can either:
  1. Use the partition export and import flow
  2. Use the design partition window menu to modify the design partition properties and turn on Ignore changes in source files and strictly use the specified netlist, if available.

As the design modification flow preserves the placement and routing from the design creation flow compilation, Intel recommends that you try the design modification flow with representative changes to ensure that the FPGA placement and routing is not adversely affected by the design creation flow place and route. Adjust the safety partition LogicLock region size and/or location, clock routing and pin placement as necessary. If you have specific pin placement and or logic placement requirements for the non-safe logic ensure these resources are reserved during the design creation flow.

To check the Intel® Quartus® Prime software acheives the expected strict preservation, for each safety IP partition check the Intel® Quartus® Prime Fitter report sub-section Incremental Compilation Placement Preservation and Incremental Compilation Routing Preservation. In the design modification flow you see entries showing that the Intel® Quartus® Prime software preserves placement and routing for the safety IP partitions.

For more information, refer to the Intel® Quartus® PrimeSoftware Handbook, chapter 3, Incremental Compilation for Hierarchical and Team based Design

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