Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.7. Daughter Cards

HPS IO48 OOBE daughter card

  • One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
  • One UART port: Standard USB Mini-B Receptacle
  • One Micro SD Card Connector: Standard Micro SD Card Socket
  • One USB 2.0 port: Standard USB Micro-AB Receptacle
  • One Mictor 38-pin connector (JTAG only without Trace signals)
  • HPS dedicated JTAG pins are connected with both mother board JTAG chain and Mictor 38pin header
  • I2C: HPS I2C port
  • GPIO
    • 2 Push buttons
    • 3 LEDs
    • 1 Ethernet Interrupt from Ethernet PHY
    • 1 USB over-current indicator
  • HPS Clock: 25 MHz oscillator

HPS IO48 NAND daughter card

  • One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
  • One UART port: Standard USB Mini-B Receptacle
  • NAND Flash (x16): 8 Gb
  • eMMC (x8): 8 GB 5.0 compliant eMMC
  • I2C: HPS I2C port
  • GPIO
    • 2 Push Buttons
    • 3 LEDs
    • 1 Ethernet Interrupt from Ethernet PHY
  • HPS Clock: 25 MHz oscillator

256MB QSPI flash daughter card

This daughter card is pre-programmed with GHRD for AS configuration. It can be re-programmed by customer image or factory provided AvST test image for AvST configuration mode. The part number is MT25QU02GCBB8E12-0SIT.

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