Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683809
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture 3. Developing Your Intel® Stratix® 10 Custom Platform 4. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Introduction to Intel® Reference Platform 1.2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform 1.4. Contents of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform
1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform x
1.3.1. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Board Variants
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture x
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® 2.2. DDR4 as Global Memory for OpenCL Applications 2.3. Host Connection to OpenCL Kernels 2.4. Partial Reconfiguration 2.5. Other Components in the Reference Design 2.6. Intel® Stratix® 10 FPGA System Design 2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows 2.9. Addition of Timing Constraints 2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.11. Intel® Stratix® 10 FPGA Programming Flow 2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® x
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access 2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP 2.1.3. Instantiation of the version_id Component 2.1.4. Board Support Package Software Layer 2.1.5. Direct Memory Access 2.1.6. Message Signaled Interrupt 2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
2.1.4. Board Support Package Software Layer x
2.1.4.1. Common Hardware Constants in Software Headers Files 2.1.4.2. PCIe Kernel Driver 2.1.4.3. Host-to-Device MMD Software Implementation
2.1.5. Direct Memory Access x
2.1.5.1. Implementing a DMA Transfer
2.2. DDR4 as Global Memory for OpenCL Applications x
2.2.1. DDR4 IP Instantiation 2.2.2. DDR4 Connection to PCIe Host 2.2.3. DDR4 Connection to the OpenCL Kernel
2.4. Partial Reconfiguration x
2.4.1. Constant Address Bridge (constant_address_bridge)
2.6. Intel® Stratix® 10 FPGA System Design x
2.6.1. Clocks 2.6.2. Resets 2.6.3. Floorplan 2.6.4. Global Routing 2.6.5. Pipelining 2.6.6. DDR4 Calibration
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design x
2.7.1. Supply the Kernel Clock 2.7.2. Guarantee Kernel Clock Timing 2.7.3. Provide a Timing-Closed Post-Fit Netlist
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows x
2.8.1. Compile Flow 2.8.2. Platform Designer System Generation 2.8.3. QAR/QDB File Generation
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ x
2.10.1. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.10.2. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
2.12.1. aocl install 2.12.2. aocl uninstall 2.12.3. aocl program 2.12.4. aocl flash 2.12.5. aocl diagnose 2.12.6. aocl list-devices
3. Developing Your Intel® Stratix® 10 Custom Platform x
3.1. Initializing Your Intel® Stratix® 10 Custom Platform 3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment 3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication 3.6. Branding Your Intel® Stratix® 10 Custom Platform 3.7. Changing the Device Part Number 3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform 3.9. Modifying the Kernel PLL Reference Clock 3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform 3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture
3. Developing Your Intel® Stratix® 10 Custom Platform
4. Document Revision History

2.2.3. DDR4 Connection to the OpenCL Kernel

The OpenCL™ kernel needs to connect directly to the memory controller in the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform via a FIFO-based clock crosser.

A clock crosser is necessary because the kernel interface for the compiler must be clocked in the kernel clock domain. In addition, the width, address width, and burst size characteristics of the kernel interface must match those specified in the OpenCL Memory Bank Divider connecting to the host. Appropriate pipelining also exists between the clock crosser and the memory controller.

To get maximum kernel clock speed for Intel® Stratix® 10 devices, custom hyper-optimized CCB and AVMM Bridge are used in this path. The CCB is in mem.qsys and the bridge is stall-free that helps in fmax. The two end points, clock crosser and logic in the kernel supports AVMM stall latency.

Important: Ensure that the WAITREQUEST_ALLOWANCE in ACL hyper-optimized CCB matches that value in board_spec.xml for that interface. The reference design BSP has one ACL hyper-optimized bridge in the static region and one in the kernel generated logic. Hence, a WAITREQUEST_ALLOWANCE value of 6 is used. Intel recommends that you leave this number as is for best performance. If you have timing closure problems, add standard Platform Designer bridges after the ACL hyper-optimized CCB in the DDR clock domain. For an additional bridge that you add, add 2 to the WAITREQUEST_ALLOWANCE.
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