Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Clock and PLL Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 1.  Clock and PLL Pins
Pin Name Pin Functions Pin Description Connection Guidelines
CLK_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]p I/O, Clock Input

Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT RD, single-ended input OCT RT, and single-ended output OCT RS are supported on these pins.

Tie the unused pins to GND or leave them unconnected.

If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

If you are using the Early I/O Release feature in the Intel® Arria® 10 SX devices, ensure that the input clock to the HPS SDRAM IP is located within the active HPS I/O banks. For more information, refer to the HPS EMIF Design Consideration chapter of the Intel® Arria® 10 SoC Design Guidelines.

CLK_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]n I/O, Clock Input

Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT RD, single-ended input OCT RT, and single-ended output OCT RS are supported on these pins.

Tie the unused pins to GND or leave them unconnected.

If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

If you are using the Early I/O Release feature in the Intel® Arria® 10 SX devices, ensure that the input clock to the HPS SDRAM IP is located within the active HPS I/O banks. For more information, refer to the HPS EMIF Design Consideration chapter of the Intel® Arria® 10 SoC Design Guidelines.

PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB[0,1] I/O, Clock Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pin. For more information about the supported pins, refer to the device pinout file.

Tie the unused pins to GND or leave them unconnected.

If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_CLKOUT[0:1] , PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_CLKOUT[0:1]p I/O, Clock I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. For more information about the supported pins, refer to the device pinout file.

Tie the unused pins to GND or leave them unconnected.

If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_CLKOUT[0:1]n I/O, Clock I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. For more information about the supported pins, refer to the device pinout file.

Tie the unused pins to GND or leave them unconnected.

If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

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