Cyclone® 10 LP Device Overview

Download PDF
ID 683879
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview x
Summary of Intel® Cyclone® 10 LP Features Intel® Cyclone® 10 LP Available Options Intel® Cyclone® 10 LP Maximum Resources Intel® Cyclone® 10 LP Package Plan Intel® Cyclone® 10 LP I/O Vertical Migration Logic Elements and Logic Array Blocks Embedded Multipliers Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O Configuration Power Management Document Revision History for Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview

FPGA General Purpose I/O

Intel® Cyclone® 10 LP devices offer highly configurable GPIOs with these features:

  • Support for over 20 popular single-ended and differential I/O standards.
  • Programmable bus hold, pull-up resistors, delay, and drive strength.
  • Programmable slew rate control to optimize signal integrity.
  • Calibrated on-chip series termination (RS OCT) or driver impedance matching (RS) for single-endd I/O standards.
  • True and emulated LVDS buffers with LVDS SERDES implemented using logic elements in the device core.
  • Hot socketing support.
Level Two Title