F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 11/03/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. HDCP Over DisplayPort Design Example 4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters 2.7. Simulation Testbench
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. HDCP Over DisplayPort Design Example
4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features

The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source.
Figure 6.  Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback without PCR
  • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned on and the video image interface is used.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor.
  • The IOPLL drives both the DisplayPort sink and source video clocks at a fixed frequency.
  • If DisplayPort sink and source's MAX_LINK_RATE parameter is configured to HBR3 and PIXELS_PER_CLOCK is configured to Quad, the video clock runs at 300 MHz to support 8Kp30 pixel rate (1188/4 = 297 MHz).
Figure 7.  Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback with AXIS Video Interface
  • In this variant, the DisplayPort source and sink parameter, select AXIS-VVP FULL in ENABLE ACTIVE VIDEO DATA PROTOCOLS to enable Axis Video Data Interface.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort Sink converts video data stream into axis video data and drives the DisplayPort source axis video data interface through VVP Video Frame Buffer. DisplayPort Source converts axis video data into DisplayPort main link before transmitting to the monitor.
  • In this design variant, there are three main video clocks, namely rx/tx_axi4s_clk, rx_vid_clk, and tx_vid_clk. axi4s_clk runs at 300 MHz for both AXIS modules in Source and Sink. rx_vid_clk runs DP Sink Video pipeline at 300 MHz (to support any resolution up to 8Kp30 4PIPs), while tx_vid_clk runs DP Source Video pipeline at the actual Pixel Clock frequency (divided by PIPs).
  • This design variant auto configures the tx_vid_clk frequency through I2C programming to on-board SI5391B OSC when the design detects a switch in the resolution.
  • This design variant only demonstrates a fixed number of resolutions as pre-defined in the DisplayPort software, namely:
    • 720p60, RGB
    • 1080p60, RGB
    • 4K30, RGB
    • 4K60, RGB
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