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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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3.4.3.1.4. hdcp2x_tx_kmem.v file
For hdcp2x_tx_kmem.v file:
- To identify the correct HDCP2 TX DCP key file for hdcp2x_tx_kmem.v, make sure the first four bytes of the file are “0x00, 0x00, 0x00, 0x01”.
- The keys in the DCP key files are in little-endian format.
- Alternatively, you can apply the lc128_prod from hdcp2x_rx_kmem.v directly into hdcp2x_tx_kmem.v. The keys share the same values.
Figure 23. Wire array of hdcp2x_tx_kmem.v
The following figure shows the exact byte mapping from HDCP2 TX DCP key file into hdcp2x_tx_kmem.v.