External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

1.2. Protocol Support Matrix

The following table lists the device family, memory protocol, and IP architecture support for the UniPHY-based external memory interface IP in the current release of the Intel® Quartus® Prime Design Suite.
Figure 2. Protocol Support Matrix  (1)  (2)  (3) (4) (5)


Notes to Table:

  1. U= Supported by UniPHY-based IP.
  2. A = Supported by ALTMEMPHY-based IP. Refer to the External Memory Interface Handbook for the Quartus II software version 12.1 or earlier for information about ALTMEMPHY-based IP.
  3. — = Not supported.
  4. The RTL-based sequencer is not available for QDR II or RLDRAM II interfaces targeting Arria® V devices.

For more information about the controllers with the Intel® UniPHY IP, refer to the Functional Descriptions section in Volume 3 of the External Memory Interface Handbook.

For more information on the Intel® MAX® 10 external memory interface IP, see Functional Description—MAX 10 EMIF IP.

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