AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6. PDN Design Optimization Study

This PDN design optimization study uses the previously determined current estimates with a sub-optimal PCB design in terms of PDN performance. It demonstrates step improvements in the PDN performance at each optimization stage. The goal is to improve the PDN efficiency as observed through an increase in the effective frequency (Feffective) for the VCC supply. It is easier to meet Ztarget with an inefficient PDN, but you should target the highest possible Feffective for your design. The VCCT_GXB and VCCR_GXB supplies have a fixed 70MHz frequency target. Optimizing the PDN results in the total number of PCB mounted decoupling capacitors being reduced. The design study discusses PCB optimization and the importance of minimizing spreading and vertical inductance in the PDN. The importance of increasing the power and ground plane capacitance is also demonstrated. Alternative capacitor technologies and their significant effect on PDN efficiency are then demonstrated resulting in fewer PCB mounted capacitors. Finally, a novel high-frequency de-rating of the VCC supply in the PDN Tool demonstrates a further dramatic reduction in the number of required decoupling capacitors.


Section Content
Initial Stackup Entry
Using the Correct Number of Power/Ground Via Pairs
Using the Correct Number of Power/Ground Via Pairs and Layer Number
Corrected Number of Power/Ground Via Pairs and Layer Numbers
Moving Supplies to Optimal Layers
Moving Power and Ground Planes Closer Together
Move Decoupling Capacitors to the Top Surface of the PCB
Using X2Y Decoupling Capacitors
Using Ultra–Low ESR Bulk Capacitors
Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4
Assessing How Much Total Capacitance Might be Required
Using the Core Clock Frequency and Current Ramp Up Period Parameters
Overall Design Study Capacitor Savings
Overall Summary
References

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