AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6.8. Using X2Y Decoupling Capacitors

As discussed, inductance is a big contributor in failing to meet target impedance at high-frequencies. The decoupling capacitors used already specify Via On Side (VOS) mounting which has lower mounting inductance (Lmnt), than Via On End (VOE). 0402 and 0201 capacitor case sizes that have lower Lmnt than 0603 or 0805 are also used. Previously, significant improvements in performance were found by increasing the number of FPGA power and ground via pairs. Using this technique with ultra-low mounting inductance X2Y capacitors can show significant improvements. The figure below shows an example of an X2Y capacitor mounting with two GND vias and four power vias. Effectively the spreading inductance of the capacitor has been reduced.

Figure 23. Example of a X2Y Capacitor Mounting with two GND Vias and Four Power Vias

Using X2Y capacitors in the PDN Tool reduces the number of capacitors required to meet the target impedance of the VCCT_GXB, and VCCR_GXB supplies from 255 and 180 to 28 and 22 respectively.

Figure 24. Capacitors Required for the VCC, VCCT_GXB, and VCCR_GXB Supplies When Using X2Y Capacitors

Using X2Y capacitors made a big improvement in the PDN efficiency. The intention of this application note was to first optimize the PCB, and then consider different capacitor technologies. The X2Y capacitors could have been used earlier in the flow, but without the underlying PCB optimization less improvement may be seen.

The impedance plots for the VCCT_GXB, and VCCR_GXB supplies shown below indicate a much cleaner impedance profile than before. The VCC supply still requires more than 301 capacitors so effort is still required to meet the target impedance.

Figure 25. VCC, VCCT_GXB, and VCCR_GXB Supply PDN Performance When Using X2Y Capacitors
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