DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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Document Table of Contents

11.4.9. DPRX0_MSA_VSP

MSA vertical synchronization polarity register, DPRX0_MSA_VSP.

Address: 0x0028

Direction: RO

Reset: 0x00000000

Table 140.  DPRX0_MSA_VSP Bits

Bit

Bit Name

Function

31:1

Unused

0

V S P

Main stream attribute vertical synchronization polarity

  • 0 = Positive
  • 1 = Negative