1.1.2. Host Interface
The host selects the SPI master by holding the CS signal high. When CS is high, the address bus bits determine to which SPI register the host is pointing. The host reads a particular register by keeping RD high and writes into a register by keeping WR high. After completing the transmission of an SPI word, the interrupt flag in the status register goes high. The host frequently monitors the status registers.
| Signal | Description |
|---|---|
| Chip select (CS) | When high, the host-to-SPI-master interface is enabled. |
| Address bus (address [1:0]) | A 2-bit address bus that selects the SPI master’s register with the corresponding address. |
| Data bus (data bus [7:0]) | An 8-bit bidirectional data bus connecting the host to the SPI master. |
| Read (RD) | When high, the host reads the SPI register whose address is being transmitted on the address bus. |
| Write (WR) | When high, the host writes into the SPI register whose address is being transmitted on the address bus. |
| Clock (CLK) | Host clock signal. |
| Address | Register | Width (Bit) |
|---|---|---|
| 00 | Control register | 8 |
| 01 | Status register | 8 |
| 10 | Transfer register | 8 |
| 11 | Receiver register | 8 |
Figure 2. Control and Status Register MapsThis figure shows the control register map and the status register map.
When an interrupt is detected, the host reads the receive buffer, writes a new command word, if required, and updates the transmit buffer. When the transmit buffer is updated, the interrupt flag in the status register is reset and a new SPI word is sent. The receive buffer is updated by the data received in this SPI word and an interrupt is again generated at the end of the word. The SPI slave select, clock polarity, clock phase, and SPI clock frequency can be controlled by the control register setting.
Figure 3. Typical SPI Timing CharacteristicsThis figure shows the typical SPI timing characteristics.