AN 485: Serial Peripheral Interface Master in Altera MAX Series

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ID 683277
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Serial Peripheral Interface Master in Altera MAX Series
1. Serial Peripheral Interface Master in Altera MAX Series x
1.1. Using SPI Master in Altera Devices 1.2. Implementation 1.3. Acknowledgments 1.4. Document Revision History
1.1. Using SPI Master in Altera Devices x
1.1.1. SPI Interface 1.1.2. Host Interface
1.2. Implementation x
1.2.1. Source Code
1. Serial Peripheral Interface Master in Altera MAX Series

1.1.1. SPI Interface

The device communicates with the slave devices using:

  • one data-out port (MOSI)
  • one data-in port (MISO)
  • clock (SCLK)
  • slave select signal (SS)
Table 1.  SPI Interface Pin DescriptionsThis table lists the pin details for the interface.
Signal Purpose Description
MOSI master-out slave-in Outputs data from the master to the inputs of the slaves.
MISO master-in slave-out Inputs data from the master to the outputs of the slaves.
SCLK SPI clock Clock driven by the master to the slaves. Synchronizes the data bits.
SS slave select Select signal (active low) is driven by the master and sent to the individual slaves. The SS signal selects the device (target slave) with which the SPI master needs to communicate. You can connect up to eight devices to the SPI master.
Note: SPI clock = host clock / (CLK DIV + 2).
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