Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Public
Document Table of Contents

3.5.7. RAM Style Attribute—For Shift Registers Inference

The RAM style attribute for shift register allows you to use the RAM style attribute for shift registers, just as you use them for RAM or ROMs. The Quartus® Prime Synthesis uses the RAM style attribute during shift register inference. If synthesis infers the shift register to RAM, it will be sent to the requested RAM block type. Shift registers are merged only if the RAM style attributes are compatible. If the RAM style is set to logic, a shift register does not get inferred to RAM.

Table 40.   Setting the RAM Style Attribute for Shift Registers
HDL Code
Verilog
(* ramstyle = "mlab" *)reg [N-1:0] sr;
VHDL
attribute ramstyle : string;attribute ramstyle of sr : signal is "M20K";