3.7.2. VHDL and Verilog HDL Messages

Quartus® Prime Standard Edition User Guide: Design Compilation

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Date 10/22/2021

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3.7.2. VHDL and Verilog HDL Messages

The Quartus® Prime software issues a variety of messages when it is analyzing and elaborating the Verilog HDL and VHDL files in your design. These HDL messages are a subset of all Quartus® Prime messages that help you identify potential problems early in the design process.

HDL messages fall into the following categories:

Info message—lists a property of your design.
Warning message—indicates a potential problem in your design. Potential problems come from a variety of sources, including typos, inappropriate design practices, or the functional limitations of your target device. Though HDL warning messages do not always identify actual problems, Altera recommends investigating code that generates an HDL warning. Otherwise, the synthesized behavior of your design might not match your original intent or its simulated behavior.
Error message—indicates an actual problem with your design. Your HDL code can be invalid due to a syntax or semantic error, or it might not be synthesizable as written.

In this example, the sensitivity list contains multiple copies of the variable i. While the Verilog HDL language does not prohibit duplicate entries in a sensitivity list, it is clear that this design has a typing error: Variable j should be listed on the sensitivity list to avoid a possible simulation or synthesis mismatch.

//dup.v
module dup(input i, input j, output reg o);
always @ (i or i)
	o = i & j;
endmodule

When processing the HDL code, the Quartus® Prime software generates the following warning message.

Warning: (10276) Verilog HDL sensitivity list warning at dup.v(2): sensitivity list contains multiple entries for "i".

In Verilog HDL, variable names are case sensitive, so the variables my_reg and MY_REG below are two different variables. However, declaring variables that have names in different cases is confusing, especially if you use VHDL, in which variables are not case sensitive.

// namecase.v
module namecase (input i, output o);
	reg my_reg;
	reg MY_REG;
	assign o = i;
endmodule

When processing the HDL code, the Quartus® Prime software generates the following informational message:

Info: (10281) Verilog HDL information at namecase.v(3): variable name "MY_REG" and variable name "my_reg" should not differ only in case.

In addition, the Quartus® Prime software generates additional HDL info messages to inform you that this small design does not use neither my_reg nor MY_REG:

Info: (10035) Verilog HDL or VHDL information at namecase.v(3): object "my_reg" declared but not used Info: (10035) Verilog HDL or VHDL information at namecase.v(4): object "MY_REG" declared but not used

The Quartus® Prime software allows you to control how many HDL messages you can view during the Analysis & Elaboration of your design files. You can set the HDL Message Level to enable or disable groups of HDL messages, or you can enable or disable specific messages.

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Quartus® Prime Standard Edition User Guide: Design Compilation

3.7.2. VHDL and Verilog HDL Messages