R-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683311
Date 4/11/2024
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1. R-Tile IP for PCI Express IP Core Release Notes
1. R-Tile IP for PCI Express IP Core Release Notes x
1.1. R-Tile IP for PCI Express IP Core v11.2.0 1.2. R-Tile IP for PCI Express IP Core v11.1.0 1.3. R-Tile IP for PCI Express IP Core v11.0.0 1.4. R-Tile IP for PCI Express IP Core v10.0.0 1.5. R-Tile IP for PCI Express IP Core v9.0.0 1.6. R-Tile IP for PCI Express IP core v8.0.0 1.7. R-Tile IP for PCI Express IP Core v7.0.0 1.8. R-Tile IP for PCI Express IP Core v6.0.0 1.9. R-Tile IP for PCI Express IP Core v5.0.0 1.10. R-Tile IP for PCI Express IP Core v4.0.0 1.11. R-Tile IP for PCI Express IP Core v3.0.0 1.12. R-Tile IP for PCI Express IP Core v2.0.0 1.13. R-Tile IP for PCI Express IP Core v1.0.0 1.14. R-Tile IP for PCI Express IP Core v1.0.0 1.15. R-Tile IP for PCI Express User Guide Archives
1. R-Tile IP for PCI Express IP Core Release Notes

1.9. R-Tile IP for PCI Express IP Core v5.0.0

Table 17.  v5.0.0 2022.03.28
Quartus® Prime Version Description Impact
22.1 Added Agilex™ 7 I-Series support for OPN suffixes R2 and R3. You can now generate and compile Quartus projects targeting the next revision of the Agilex™ 7 I-Series OPNs.
Enabled Port2 in 4x4 configuration.

Port 2 is now enabled in the 4x4 configuration for devices with the suffixes R2 or R3 in their OPN numbers. For additional details on OPN decoding, refer to the Agilex™ 7 FPGAs and SoCs Device Overview.

Added support for more data bus widths and PLD clock frequencies.

Additional data bus widths and clock frequencies are available for the Application logic in Gen4 and Gen3 configurations. For additional details, refer to Table 49 in Avalon Streaming Interface Data and Header Bus Widths per Port.
Added support for VirtIO for Port 2 and Port 3 in a 4x4 configuration. This additional VirtIO support is only available in devices with the suffixes R2 or R3 in their OPN numbers. For additional details on OPN decoding, refer to the Agilex™ 7 FPGAs and SoCs Device Overview.
Table 18.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP UP/DN -1 -2 -3
16-channel PIPE Direct N/A N/A N/A 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen4 x16 512-bit (*) SCT SCT SCT 500 MHz 500 MHz N/A
Gen3 x16 512-bit (*) SCT SCT SCT 500 MHz 500 MHz N/A
Gen5 x8/x8 512-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen4 x8/x8 256-bit (*) SCT SCT SCT 500 MHz 500 MHz N/A
Gen3 x8/x8 256-bit (*) SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen3 x4/x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen4 x4/x4/x4/x4 128-bit (*) SCT SCT SCT 500 MHz 500 MHz N/A
Gen3 x4/x4/x4/x4 128-bit (*) SCT SCT SCT 300 MHz 300 MHz 300 MHz
Note: (*) These configurations are only available in devices with the suffix R2 in their OPN numbers. For additional details on OPN decoding, refer to Agilex™ 7 FPGAs and SoCs Device Overview.
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