Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. LL 100GbE Design Example Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design Example in Hardware
2. LL 100GbE Design Example Description x
2.1. Features 2.2. Software and Hardware Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Design Example Registers
2.4. Design Variations x
2.4.1. Standard CAUI IP Core Variation 2.4.2. CAUI-4 IP Core Variation
1. Quick Start Guide
2. LL 100GbE Design Example Description
A. Document Revision History

2.4.2. CAUI-4 IP Core Variation

The design example for CAUI-4 variations configures two ATX PLLs and connects the output tx_serial_clk signal of each ATX PLL to two of the four IP core transceiver channels. The required ATX PLL output frequency only supports a fanout of two. If this arrangement is not available for your design, you can use additional external ATX and CMU PLLs to generate and distribute the tx_serial_clk signals for the individual channels.
Figure 9. CAUI-4 IP Core Variation Testbench
The simulation testbench instantiates the IP core and necessary PLLs. It interfaces directly with the Avalon-ST port to provide basic packet sending and receiving. The TX and RX lanes can be connected together to provide loopback testing capabilities.
Level Two Title