Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. LL 100GbE Design Example Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design Example in Hardware
2. LL 100GbE Design Example Description x
2.1. Features 2.2. Software and Hardware Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Design Example Registers
2.4. Design Variations x
2.4.1. Standard CAUI IP Core Variation 2.4.2. CAUI-4 IP Core Variation
1. Quick Start Guide
2. LL 100GbE Design Example Description
A. Document Revision History

A. Document Revision History

Table 7.  Revision History
Date Changes
2017.11.08 Added link to KDB Answer that provides workaround for potential jitter on Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Generating the Design and Compiling and Testing the Design Example in Hardware.
Note: This design example user guide has not been updated to reflect minor changes in design generation in Quartus® Prime releases later than the Quartus® Prime software relase v16.1.
2016.11.23
  • Updated for Quartus® Prime software v16.1. Refer to Directory Structure and various Related References links updated for the separation of the Low Latency 100-Gbps Ethernet IP Core User Guide from the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core User Guide.
  • Updated to refer to design example rather than example design.
  • Corrected assorted typos and minor errors.
2016.05.02 Initial release
Level Two Title