Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. LL 100GbE Design Example Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design Example in Hardware
2. LL 100GbE Design Example Description x
2.1. Features 2.2. Software and Hardware Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Design Example Registers
2.4. Design Variations x
2.4.1. Standard CAUI IP Core Variation 2.4.2. CAUI-4 IP Core Variation
1. Quick Start Guide
2. LL 100GbE Design Example Description
A. Document Revision History

2.6. Design Example Registers

Table 5.  Hardware Design Example Register MapLists the memory mapped register ranges for the LL 100GbE hardware design example.

Word Offset

Register Category

0x1000–0x1016

Packet client registers

0x2004–0x2023

Reserved

0x4000–0x4C00

 Arria 10 dynamic reconfiguration register base addresses for CAUI-4 (four-lane) variations. Register base address is 0x4000 for Lane 0, 0x4400 for Lane 1, 0x4800 for Lane 2, and 0x4C00 for Lane 3. (Bits [11:10] specify the lane).

0x4000–0x6400

 Arria 10 dynamic reconfiguration register base addresses for standard (ten-lane) variations. Register base address is 0x4000 for Lane 0, 0x4400 for Lane 1, 0x4800 for Lane 2, and 0x4C00 for Lane 3, 0x5000 for Lane 4, ... 0x6400 for Lane 9. (Bits [13:10] specify the lane).
Table 6.  Packet Client Registers You can customize the LL 100GbE hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string "CLNT" RO
0x1002 PKT_CL_FEATURE [9:0] Feature vector to match DUT. Bits [8:3] have the value of 0 to indicate the DUT does not have the property or the value of 1 to indicate the DUT has the property.
  • Bit [0]: Has the value of 1 to indicate the DUT targets an Arria 10 device.
  • Bit [1]: Has the value of 1 to indicate that the DUT is a LL 100GbE IP core.
  • Bit [2]: Reference clock frequency. Has the value 0 for 322 MHz; has the value of 1 for 644 MHz.
  • Bit [3]: Reserved.
  • Bit [4]: Indicates whether the DUT is a CAUI-4 IP core.
  • Bit [5]: Indicates whether the DUT includes PTP support.
  • Bit [6]: Indicates whether the DUT includes pause support.
  • Bit [7]: Indicates whether the DUT provides local fault signaling.
  • Bit [8]: Indicates whether the DUT has Use external MAC TX PLL turned on. Must have the value of 0.
  • Bit [9]: Value 0 if the DUT has a custom streaming client interface; value 1 if the DUT has an Avalon-ST client interface. Must have the value of 1.
RO
0x1006 PKT_CL_TSD [7:0] Arria 10 device temperature sensor diode readout in Fahrenheit. RO
0x1010 PKT_GEN_TX_CTRL [3:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
4'b0101 RW
0x1015 PKT_CL_LOOPBACK_FIFO_ERR_CLR [2:0] Reports MAC loopback errors.
  • Bit [0]: FIFO underflow. Has the value of 1 if the FIFO has underflowed. This bit is sticky. Has the value of 0 if the FIFO has not underflowed.
  • Bit [1]: FIFO overflow. Has the value of if the FIFO has overflowed. This bit is sticky. Has the value of 0 if the FIFO has not overflowed.
  • Bit [2]: Assert this bit to clear bits [0] and [1].
3'b0 RO
0x1016 PKT_CL_LOOPBACK_RESET [0] MAC loopback reset. Set to the value of 1 to reset the design example MAC loopback. 1'b0 RW
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