Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.11.1. Interrupt Interface

If you enable the Avalon® Memory Mapped Slave interface, you can use the optional interrupt interface of the Intel® Arria® 10 FPGA IP.

The IP core asserts irq during the following events:

Table 12.  Interrupt Interface Events
Status Code Event
3'b001 PR_ERROR occurred.
3'b010 CRC_ERROR occurred.
3'b011 The IP core detects an incompatible bitstream.
3'b101 The result of a successful PR operation.

After irq asserts, the master performs one or more of the following:

  • Query for the status of the PR IP core; PR_CSR[4:2].
  • Carry out some action, such as error reporting.
  • Once the interrupt is serviced, clear the interrupt by writing a "1" to PR_CSR[5].
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