1.8. Partial Reconfiguration IP Core Parameters
| IP Core Option | Value | Default | Description |
|---|---|---|---|
| Use as PR internal host |
On or Off |
On |
Turn on this option to use the PR IP core as an internal host. Both prblock and crcblock WYSIWYG atom primitives are auto-instantiated as part of your design. Disable this option to use the PR IP core as an external host in an external device. You must connect additional interface signals to the dedicated PR pins if you use the PR IP core as an external host. |
| Enable JTAG debug mode |
On or Off |
On |
To perform partial reconfiguration turn on this option to access the PR IP core with the Programmer. |
| Enable Avalon-MM slave interface | On or Off |
Off |
Turn on this option to use the Avalon Memory-Mapped (Avalon-MM) slave interface. |
| Enable interrupt interface | On or Off |
Off |
Enable this option to use the interrupt interface. You can only enable this interface if you turned on the Enable Avalon-MM slave interface parameter. |
| Enable bitstream compatibility check | On or Off |
Off |
Turn on this option to check the bitstream compatibility during PR operations for external host. The bitstream compatibility check feature is always enabled for PR internal host. Specify the PR bitstream ID value if you enable this option for PR external host. |
| PR bitstream ID |
-2147483648 to 2147483647 |
0 |
Specifies a signed 32-bit integer value of the PR bitstream ID for external host. This value must match the PR bitstream ID generated during compilation for the target PR design. You can find the PR bitstream ID value of the target PR design in the Assembler compilation report (.asm.rpt). |
| Input data width |
1, 8, 16, or 32 |
16 |
Specifies the data width in bits. This option affects the data[] bus width. |
| Target device family for partial reconfiguration |
Cyclone V, Stratix® V |
" Stratix® V" |
Select the target device family for partial reconfiguration when you use the PR IP core as external host.
Note: This option is ignored for PR internal host.
|
| Clock-to-Data ratio |
Cyclone V or Stratix® V:1, 2, or 4 |
1 |
Specifies the ratio between PR clock and PR data. s |
| Divide error detection frequency by |
1, 2, 4, 8, 16, 32, 64, 128, or 256 |
1 |
Only available when you use the IP core as an internal host. The crcblock WYSIWYG atom primitive is auto-instantiated as part of the design. Specifies the divide value of the internal clock, which determines the frequency of the error detection cyclic redundancy check (CRC). The divide value must be a power of two. Refer to the device handbook to find the frequency of the internal clock for the selected device. |
| Auto-instantiate CRC block |
On or Off |
On |
This option is only applicable for an internal host. Disable this option to manually instantiate a CRC block. |
| Auto-instantiate PR block |
On or Off |
On |
This option is only applicable for an internal host. Disable this option to manually instantiate a PR block. |
| Enable enhanced decompression |
On or Off |
Off |
Enable this option is to use the enhanced decompressor. Decompress bitstreams that are compressed with the enhanced compression algorithm. |