Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.11. Slave Interface

The Partial Reconfiguration Controller IP core provides an Avalon® -MM slave interface to read and write to PR configuration registers.

Table 10.  Data/CSR Memory Map Format
Name Address Offset Access Description
PR_DATA 0x00 Write

Every data write to this address indicates this bitstream is sent to the IP core.

Performing a read on this address returns all 0's.

PR_CSR 0x01 Read or Write Control and status registers.
Version Register 0x02 Read-Only

Read-only SW version register. Register is currently 0xAA500003
PR Bitstream ID 0x03 Read-Only Read-only PR POF ID register
Table 11.  PR_CSR Control and Status Registers
Bit Offset Description
0

Read and write control register for pr_start signal. Refer to Input/Output Port List section for more details on the pr_start signal.

pr_start = PR_CSR[0]

The IP core deasserts PR_CSR[0] to value 0 automatically, one clock cycle after the PR_CSR[0] asserts. This streamlines the flow to avoid manual assertion and de-assertion of this register to control pr_start signal.

1

Read and write control register for double_pr signal.

double_pr = PR_CSR[1]

2-4

Read-only status register for status[2:0] signal.

PR_CSR[4:2] = status[2:0]

5

Read and clear bit for interrupt.

If you enable the interrupt interface, reading this bit returns the value of the irq signal. Writing a 1 clears the interrupt.

If you disable the interrupt interface, reading this bit always returns a value of 0.

6-15 Reserved bits. Depends on the Avalon® -MM data bus width. When you use enhanced compression, data width limits to 16.
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