AN 495: IDE/ATA Controller Using Altera MAX Series

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ID 683523
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. IDE/ATA Controller Using Altera MAX Series
1. IDE/ATA Controller Using Altera MAX Series x
1.1. IDE/ATA Controller and Interface 1.2. IDE/ATA Controller Using Supported Altera Devices 1.3. Implementation 1.4. Acknowledgments 1.5. Document Revision History
1.2. IDE/ATA Controller Using Supported Altera Devices x
1.2.1. CPU Interface Block 1.2.2. PIO Controller Block 1.2.3. IDE Interface Block
1. IDE/ATA Controller Using Altera MAX Series

1.2.1. CPU Interface Block

The CPU interface block receives the signals from the host CPU and stores them in the internal registers of the supported Altera device. Depending on the information in these internal registers, the PIO controller goes through the various states of the PIO read and write operations.

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