AN 495: IDE/ATA Controller Using Altera MAX Series

ID 683523
Date 9/22/2014
Public

1.1. IDE/ATA Controller and Interface

When controllers and hard drives had proprietary technologies, a controller from one manufacturer did not work well with a hard drive from another manufacturer. The IDE was created to standardize the use of hard drives in computers. This was based on a concept of combining the controller and the hard drive, thereby reducing interface costs and making firmware implementations easier. The controller residing on a chip provided the means for transferring data to or from the host computer.

This IDE controller, also known as the ATA (Advanced Technology Attachment) controller, is an asynchronous parallel interface between a host microprocessor system and a standard IDE device. Therefore, this can be called a host adapter because it provides a way to connect a complete IDE device to the host.

From the time of its inception, the ATA interface has been upgraded frequently and newer versions have been introduced. This design example implements an IDE controller compatible with the ATA-5 interface. The ATA-5 standard supports the following modes of operation:

  • The PIO mode
  • The DMA mode

Although the ATA-5 standard supports two modes, this design is restricted to only the PIO mode (mode 0) and with only one device connected to the controller (master).

Figure 1. Basic Block Diagram of an IDE/ATA InterfaceThe IDE/ATA interface consists of three blocks—the CPU interface block that receives commands from the CPU, the PIO controller block that contains the PIO state machine, and the IDE interface block that generates the signals required by the IDE device to carry out data transfer with the host (computer).