AN 495: IDE/ATA Controller Using Altera MAX Series

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ID 683523
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. IDE/ATA Controller Using Altera MAX Series
1. IDE/ATA Controller Using Altera MAX Series x
1.1. IDE/ATA Controller and Interface 1.2. IDE/ATA Controller Using Supported Altera Devices 1.3. Implementation 1.4. Acknowledgments 1.5. Document Revision History
1.2. IDE/ATA Controller Using Supported Altera Devices x
1.2.1. CPU Interface Block 1.2.2. PIO Controller Block 1.2.3. IDE Interface Block
1. IDE/ATA Controller Using Altera MAX Series

1.2.3. IDE Interface Block

This IDE interface block generates the appropriate interfacing signals so that the data is loaded into or from the addressed internal register of the IDE device. The internal register selected depends on the value of the da[2:0], cs0n, and cs1n lines. A read or write operation is indicated by the diorn and the diown lines, respectively.

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