HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Public
Document Table of Contents

9.2.2.7. VIDEO_MODE_F1_LINE_COUNT (0x57)

Table 107.  VIDEO_MODE_F1_LINE_COUNT (0x57)
Name Bit(s) Access Description Reset
Reserved 31:16
F1 line count 15:0 RW Specifies the active picture height of interlaced video field 1. 0x0