Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 5/14/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Testing the Functionality of the Development Kit 4.3. Controlling the On-board Clock through Clock Controller GUI 4.4. Monitoring On-Board Power Regulator through Power Monitor GUI 4.5. Identifying Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Testing the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.3. Controlling the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the Avalon® streaming interface x8 configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.2. Clocks

Table 6.  Default Clock Frequency
Schematic Signal Name Default Frequency (MHz)
SAMPLE_CLK_312_50MHZ_P/N 312.50
TOD_MASTER_156_25MHZ_P/N 156.25
1PPS_SI5518 100
SI5518_10MHZ_OUT 10
CLK_156_25MHZ_5391_P/N 156.25
CLK_390_625MHZ_1P/1N 390.625
CLK_390_625MHZ_2P/2N 390.625
CLK_390_625MHZ_3P/3N 390.625
CLK_3_84MHZ_SMA_P/N 3.84
CLK_245_76MHZ_SMA_P/N 245.76
CLK_245_76MHZ_1P/1N 245.76
CLK_245_76MHZ_2P/2N 245.76
CLK_245_76MHZ_3P/3N 245.76
CLK_245_76MHZ_4P/4N 245.76
CLK_390_625MHZ_4P/4N 390.625
CLK_390_625MHZ_5P/5N 390.625
CLK_156_25MHZ_U22_P/N 156.25
CLK_156_25MHZ_1_FMC_P/N 156.25
CLK_156_25MHZ_2_FMC_P/N 156.25
CLK_156_25MHZ_3_FMC_P/N 156.25
CLK_156_25MHZ_4_U22_P/N 156.25
CLK_156_25MHZ_5_U22_P/N 156.25
CLK_156_25MHZ_6_U20_P/N 156.25
CLK_156_25MHZ_7_U20_P/N 156.25
CLK_156_25MHZ_8_FMC_CON_P/N 156.25
CLK_156_25MHZ_SI5391_1_P/N 156.25
CLK_156_25MHZ_SYNCE_DDR_P/N 156.25
CLK_156_25_MHZ_SI5392 156.25
CLK_UIB0_P/N 100
CLK_UIB0_FBR0_P/N 100
CLK_UIB0_FBR1_P/N 100
CLK_UIB1_P/N 100
FPGA_IO_CLK0_P/N 100
FPGA_IO_CLK5_P/N 100
CLK_UIB1_FBR0_P/N 100
CLK_UIB1_FBR1_P/N 100
CLK_100M_RP_0_P/N 100
CLK_100M_PCIE1_P/N 100
CLK_100M_PCIE0_P/N 100
CLK_100M_RP_1_P/N 100
CLK_100M_RP_2_P/N 100
CLK_SI5332_U10_IO_PLL_DP 100
CLK_SI5332_U20_IO_PLL_DP 100
CLK_SI5332_U22_IO_PLL_DP 100
CLK_DDR5_RDIMM_A0_DP/DN 100
CLK_DDR5_RDIMM_A1_DP/DN 100
CLK_DDR5_COM_DP/DN 100
CLK_DDR5_COM_HPS_DP/DN 100
CLK_LP5_B1_P/N 100
CLK_LP5_A1_P/N 100
FPGA_IO_CLK_2_P/N 100
CLK_NOC_PLL0 100
CLK_NOC_PLL1 100
FPGA_SDM_1V8_125M_CLK 125
Figure 27. Clock Tree
Level Two Title