Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 5/14/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Testing the Functionality of the Development Kit 4.3. Controlling the On-board Clock through Clock Controller GUI 4.4. Monitoring On-Board Power Regulator through Power Monitor GUI 4.5. Identifying Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Testing the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.3. Controlling the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the Avalon® streaming interface x8 configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.5. Communication Interfaces

MCIO Port

The MCIO slot is a PCIe* Gen4 x4 port which fans out from Agilex™ 7 FPGA M-Series F-Tile. This port is designed to meet the standard MCIO pinout. PCIE1_PERST0_N signal can act as output and input respectively.

Table 9.  MCIO Port
Schematic Signal Name Description
PCIE_PERSTn_A PCIe* endpoint/root port reset
PCIE_ALERTn_A PCIe* Alert
PCIE_100M_REF_AP/AN PCIe* reference clock
PCIE_SCL_A/SDA_A PCIe* I2C bus
PCIE_TX_P/N[15:0] Transceiver TX
PCIE_RX_P/N[15:0] Transceiver RX

2x MCIO x8 Connector

The recommended MCIO cable to use with MCIO connector (Uxx) is not included as part of the development kit and must be acquired directly from third party supplier (Amphenol p/n = HMC74-0631).

QSFPDD

The Agilex™ 7 M-Series Development Kit supports 2x QSFPDD ports. The QSFDD port fans out from Agilex™ 7 FPGA M-Series F-Tile (FGT). All 8 channels per QSFPDD can run up to 32G NRZ and 58G PAM4.

QSFPDD800

The Agilex™ 7 M-Series Development Kit supports 1X QSFPDD800 port. The QSFDD800 port fans out from Agilex™ 7 FPGA M-Series F-Tile (FHT). All 8 channels per QSFPDD800 can run up to 32G NRZ, 58G PAM4, and 116G.

Table 10.  QSFPDD Connector 0 (J16)
Schematic Signal Name Description
QSFPDD0_3V3_MODPRS_L Module present
QSFPDD0_3V3_RESET_L Module reset
QSFPDD0_3V3_MODSEL_L Mode select
QSFPDD0_3V3_LPMODE Initial mode
QSFPDD0_3V3_INT_L Interrupt
I2C_QSFPDD0_3V3_SCL I2C clock
I2C_QSFPDD0_3V3_SDA I2C data
QSFPDD0_TX_P/N[0:7] Transceiver TX
QSFPDD0_RX_P/N[0:7] Transceiver RX
Table 11.  QSFPDD Connector 1 (J17)
Schematic Signal Name Description
QSFPDD1_3V3_MODPRS_L Module present
QSFPDD1_3V3_RESET_L Module reset
QSFPDD1_3V3_MODSEL_L Mode select
QSFPDD1_3V3_LPMODE Initial mode
QSFPDD1_3V3_INT_L Interrupt
I2C_QSFPDD1_3V3_SCL I2C clock
I2C_QSFPDD1_3V3_SDA I2C data
QSFPDD1_TX_P/N[0:7] Transceiver TX
QSFPDD1_RX_P/N[0:7] Transceiver RX
Table 12.  QSFPDD800 (J18)
Schematic Signal Name Description
QSFPDD800_3V3_MODPRS_L Module present
QSFPDD800_3V3_RESET_L Module reset
QSFPDD800_3V3_MODSEL_L Mode select
QSFPDD800_3V3_LPMODE Initial mode
QSFPDD800_3V3_INT_L Interrupt
I2C_QSFPDD800_3V3_SCL I2C clock
I2C_QSFPDD800_3V3_SDA I2C data
QSFPDD800_TX_P/N[0:3] Transceiver TX
QSFPDD800_RX_P/N[0:3] Transceiver RX

FMC+ Connector

The Agilex™ 7 M-Series Development Kit supports FMC+ slots for functional expandability. The x16 FGT lanes from bank 12A are terminated to the FMC+ (J34) connector and the 64 I/O signals from bank 2A connect to the FMC+ (J34) connector. Auxiliary signals are controlled by the system MAX® 10.

USB Type-C Connector

The Agilex™ 7 M-Series Development Kit has hardware support for the USB Type-C connector, which supports DP1.4 specification or USB 3.1 functionality through MUX (TUSB1146). This feature is yet to be validated and implemented.

Serial Buses

The SDM I/Os (SDM_IO16/0) and MAX® 10 I/Os (VCCL_SDA/SCL) share the same I2C bus which communicate with Agilex™ 7 FPGA core regulators. By default, SDM acts as SmartVID master and system MAX® 10 act as Power GUI master in this chain.

The system MAX® 10 I/Os (PMB_SDA/SCL) manages the second I2C bus which access all I2C slave regulator except Agilex™ 7 FPGA core regulators.

The system MAX® 10 supports I2C master dedicated to clock-related devices (CLK_I2C_SDA/SCL), which manages 3# clock devices and also connected to the HPS I/Os (HPS_GPIO30/31) through level translator.

Another I2C master instance from the system MAX® 10 (VCXO_I2C_SDA/SCL) controls the on board VCXO and Si5394 clock generator.

The Agilex™ 7 FPGA also manages QSFPDD800, 2x QSFPDD, 1 RDIMM DDR5 I2C buses, SDI transceivers, and ZL30733 clock synthesizer device.

Table 13.   I2C Debug Headers
Schematic Signal Name Description
PMB_SCL/SDA VRs I2C header J5 and J91
CLK_I2C_SDA/SCL_3V3 All clock devices I2C header J40
HPS_SCL/HPS_SDA HPS I2C interface MAX® 10

FMC_SCL_1V2

FMC_SDA_1V2

FMC+ I2C interface Agilex™ 7 M-Series HBM2e

FP_I3C_2C_DIMM_SCL

FP_I3C_2C_DIMM_SDA

DDR5_I3C_RDIMM interface Agilex™ 7 M-Series HBM2e

MAX10_I2C_2C_DIMM_SCL

MAX10_I2C_2C_DIMM_SDA

DDR5_I3C_RDIMM interface Agilex™ 7 M-Series HBM2e

I2C_PWR2_SCL

I2C_PWR2_SDA

Agilex™ 7 M-Series HBM2e R-Tile die, 3 F-Tile die, I/O core die board temperature sense, I2C interface MAX® 10
FX2_SCL/FX2_SDA USB PHY I2C interface MAX® 10
MAX2237B_SCL/SDA SI569_148.50 MHz interface MAX® 10 can adjust the frequency for FMC+Video interface card
Table 14.  SPI Debug Headers for SI5518 Clocks
Schematic Signal Name Description
FPGA_SI5518_1V8_GPIO3 Si5518 SPI BUS, Debug connector J22 and J41
FPGA_SI5518_A0_1V8_CSB
I2C_1V8_CLK_GUI_SDA
I2C_1V8_CLK_GUI_SCL
Figure 28.  I2C Serial Bus
Level Two Title