F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

ID 792946
Date 12/04/2023
Public
Document Table of Contents

8.5. Hard IP Registers

The Ethernet Reconfiguration interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® memory-mapped interface space. All addresses are byte-based addresses eventhough the register description specifies 32 bit boundary. Refer to the F-Tile Ethernet Hard IP Register Map to view the register map and register descriptions.

The Transceiver Reconfiguration interface provides access to the control and status registers of the Intel Agilex® 7 F-Tile transceiver. Refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide for information about the transceiver register map and register descriptions.

Table 24.  Hard IP Registers
Address Name Description Access
0x0104 qhip_scratch Scratch register. 32 bits of scratch register space for testing. RW
0x010C eth_reset_status IP reset status register. Not sticky bit, Includes the following fields:
  • Bit[0]: rst_ack_n
  • Bit[1]: tx_rst_ack_n
  • Bit[2]: rx_rst_ack_n
RO
0x0110 o_tx_pll_locked TX PLL locked bit [7:0]. TX PLL used by the corresponding physical lane is locked. RO
0x0118 pcs_status PCS status. Includes the following field:
  • Bit[2]: tx_lanes_stable
  • Bit[3]: rx_pcs_ready
RO
0x0128 clk_tx_khz i_clk_tx clock frequency in KHz. RO
0x012C clk_rx_khz i_clk_rx clock frequency in KHz. RO
0x0130 clk_pll_khz o_clk_pll clock frequency in KHz. RO
0x0134 clk_tx_div_khz o_clk_tx_div clock frequency in KHz. RO
0x0138 clk_rec_div64_khz o_clk_rec_div64 clock frequency in KHz. RO
0x013C clk_rec_div_khz o_clk_rec_div clock frequency in KHz. RO
0x6070 e25g_s0_xcvrif_reg_12 TX-RX loopback enable. This does not include UX/BK mapping. Includes the following field:
  • Bit[0]: lpbk_en
RW