F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

ID 792946
Date 12/04/2023
Public
Document Table of Contents

7.6. Miscellaneous Status and Debug Signals

The miscellaneous status and debug signals are asynchronous.
Table 14.  Miscellaneous Status and Debug Signals

Signal

Direction

Description

tx_lanes_stable Output Active-high asynchronous status signal for the TX datapath.
  • Asserts when the TX datapath is ready to send data.
  • Deasserts when i_tx_rst_n/i_rst_n signal asserts.
rx_block_lock Output

By default, the Enable RS-FEC in the parameter editor is turned off. This signal is asserted when the IP completes 66-bit block boundary alignment on all PCS lanes.

rx_pcs_ready Output Active-high asynchronous status signal for the RX datapath.
  • Asserts when the RX datapath is ready to receive data.
  • Deasserts when i_rx_rst_n/i_rst_n signal asserts or during the auto-negotiation and link training operation.
rx_am_lock Output Asserted when all lanes have identified alignment markers in the data stream.
local_fault_status Output Asserted when the RX MAC detects a local fault. This signal is available if you turn on Enable link fault generation in the parameter editor.
o_remote_fault_status Output Asserted when the RX MAC detects a remote fault. This signal is available if you turn on Enable link fault generation in the parameter editor.
unidirectional_en Output Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.
link_fault_gen_en Output Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.