AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

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ID 683020
Date 6/13/2017
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design x
Reference Design Components Reference Design Folders and Files Quick Start Guide Rebuilding the Nios II Software Reference Design Debug Features Known Issues Revision History
Reference Design Components x
Clocking Scheme DisplayPort IP Core Video and Image Processing Block External Memory Interface Nios II Processor Transceiver Push Buttons and LEDs
Quick Start Guide x
Hardware and Software Requirements Compiling and Running the Reference Design Viewing the Result
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

Clocking Scheme

The reference design requires several clock sources from the FPGA development kit and the FMC daughter card for proper operation. The reference design uses the default clock frequency from the oscillator; no programming is required through the Clock Control application.
Table 2.  Clock Signals
Signal Description Pin Number I/O Standard Usage
refclk1_p

External 100 MHz clock from X3 programmable oscillator on the FPGA development kit.

AG37/AG38 LVDS
  • Avalon-MM interface for DisplayPort and VIP IP cores
  • Transceiver reconfiguration interface
  • TX and RX Bitec reconfiguration management
  • Transceiver reconfiguration arbiter
  • Intel PHY reset controller
  • TX PLL and TX/RX transceiver channel reconfiguration interfaces
  • Nios II CPU and peripherals
  • Video PLL (IO PLL) input reference clock
fmca_gbtclk_m2c_p

External 135 MHz clock from Bitec FMC daughter card. The oscillator is not programmable.

AL8/AL7 LVDS
  • TX PLL input reference clock
  • RX CDR input reference clock
mem_pll_ref_clk

External 133 MHz clock from U26 programmable oscillator on the FPGA development kit.

F34/F35 LVDS DDR4 external memory interface input reference clock
dp_tx_vid_ clk

Generated 133.33 MHz clock from video PLL.

   – DisplayPort Source–Clocked Video Output interface
dp_rx_vid_ clk

Generated 160 MHz clock from video PLL.

 – –
  • DisplayPort Sink–Clocked Video Output interface
  • Avalon-ST video data path
clk_16

Generated 16MHz clock from video PLL

– –
  • DisplayPort Sink and Source 1 Mbps AUX channel interface
  • DisplayPort Sink and Source AUX debug FIFO
clk_cal

Derived 50MHz clock from refclk1

 – – DisplayPort Sink and Source calibration. This clock must be synchronous to the clock used for the transceiver reconfiguration block (100 MHz)
The 160 MHz clock output from the video PLL drives the DisplayPort Sink and Clocked Video Input interface. This interface runs at input video pixel clock domain; this clock frequency must be equal or greater than the required pixel clock frequency of the input video stream.
Note: The ANSI/CEA-861-F standard requires the 3840 × 2160 @ 60 Hz video stream to run at 594.0 MHz pixel clock. This design uses 4 pixels per clock so that the interface runs at 148.5 MHz (quarter rate of 594.0 MHz), but with 4 times video bus width between the DisplayPort Sink and Clocked Video Input. Because 160 MHz is higher than 148.5 MHz, this frequency is sufficient to support 4Kp60 input video stream.

The 133.33 MHz clock output from the video PLL drives the DisplayPort Source and Clocked Video Output interface. The CVT-RB specification states that the 133.33 MHz should be derived from the reduced blanking period of the 4K video output stream.

Table 3.  4Kp60 Video Stream Timing Information for Normal and Reduced Blanking
H Active × V Active H Total H Blank V Total V Blank Pixel Frequency
Normal 4,400 560 2,250 90 594.00 MHz
Reduced 4,000 160 2,222 62 533.28 MHz
This design uses 4 pixels per clock so that the interface runs at 133.33 MHz (quarter rate of 533.28 MHz), but with 4 times wider video bus between the DisplayPort Source and Clocked Video Output.
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