AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

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ID 683020
Date 6/13/2017
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design x
Reference Design Components Reference Design Folders and Files Quick Start Guide Rebuilding the Nios II Software Reference Design Debug Features Known Issues Revision History
Reference Design Components x
Clocking Scheme DisplayPort IP Core Video and Image Processing Block External Memory Interface Nios II Processor Transceiver Push Buttons and LEDs
Quick Start Guide x
Hardware and Software Requirements Compiling and Running the Reference Design Viewing the Result
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

Nios II Processor

The DisplayPort Source and Sink require a processor (e.g. Nios II processor) to act as link policy maker.

The design requires the Enable GPU Control option for the DisplayPort Sink to be turned on.

The Nios II processor performs the following functions:
  • Runs software that acts as a DisplayPort link policy maker.
  • Provides access to the DisplayPort IP core status and debug registers.
  • Retrieves AUX channel transaction logs from the DisplayPort Source and Sink AUX debug FIFO.
  • Monitors push buttons to print Main Stream Attribute (MSA) values and AUX channel transaction logs to the Nios II terminal.
  • Initializes the VIP Suite IP cores.
Level Two Title