AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

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ID 683020
Date 6/13/2017
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design x
Reference Design Components Reference Design Folders and Files Quick Start Guide Rebuilding the Nios II Software Reference Design Debug Features Known Issues Revision History
Reference Design Components x
Clocking Scheme DisplayPort IP Core Video and Image Processing Block External Memory Interface Nios II Processor Transceiver Push Buttons and LEDs
Quick Start Guide x
Hardware and Software Requirements Compiling and Running the Reference Design Viewing the Result
Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

Reference Design Folders and Files

All the relevant design files reside in the project folder.
Table 9.  
Folder/File Name Description
rtl/core/altera_avalon_i2c

Contains I2C master source files. I2C master is not used in this reference design.

rtl/core/dp_core

Contains the generated IP files and subfolders in dp_core.qsys of the Qsys system.

rtl/core/ip/dp_rx

Contains the generated IP files and subfolders in dp_rx.qsys of the Qsys subsystem

Note: Only for Quartus® Prime Pro Edition.
rtl/core/ip/dp_tx

Contains the generated IP files and subfolders in dp_tx.qsys of the Qsys subsystem.

Note: Only for Quartus® Prime Pro Edition.
rtl/core/ip/vip

Contains the generated IP files and subfolders in vip.qsys of the Qsys subsystem.

Note: Only for Quartus® Prime Pro Edition.
master_image

Contains precompiled .sof and .elf files.

rtl/rx_phy/gxb_rx

Contains generated RX PHY IP files.

rtl/rx_phy/gxb_rx_reset

Contains generated RX PHY reset controller IP files.

rtl/tx_phy/gxb_tx

Contains generated TX PHY IP files.
rtl/tx_phy/gxb_tx_fpll

Contains generated TX fPLL IP files.
rtl/tx_phy/gxb_tx_reset

Contains generated RX PHY reset controller IP files.

rtl/i2c_gpio_buf

Contains generated IO buffer IP files for the I2C master interface. I2C master is not used in this reference design.

rtl/video_pll_a10

Contains generated IO PLL IP files for video PLL.

software

Contains the Nios II software project. The dp_demo.zip file contains the software project; the dp_demo folder contains the .qip and .hex files of the software project.

tcl

Contains the TCL script for debugging purpose.

software/main.c , software/rx_utils.c , software/tx_utils.c , software/tx_utils.h , software/config.h , and software/vip.h

These are the C source code and header files. You can customize these files for your applications. These files will be copied to the software folder when you run the build_sw.sh script.

top.qpf and top.qsf

The Quartus Prime project and setting files for this reference design.

rtl/core/dp_core.qsys , rtl/core/dp_rx.qsys , rtl/core/dp_tx.qsys , and rtl/core/vip.qsys
The dp_core.qsys file belongs to the top level Qsys system. The dp_rx.qsys file belongs to the DisplayPort RX Qsys subsystem, the dp_tx.qsys file belongs to the DisplayPort TX Qsys subsystem, and the vip.qsys file belongs to the VIP Qsys subsystem. The design includes the dp_rx.qsys, dp_tx.qsys, and the vip.qsys files so that dp_core.qsys loads correctly into Qsys.
Note: For Quartus® Prime Standard Edition designs, do not include the dp_rx.qsys, dp_tx.qsys, and vip.sys files in the top.qsf file to avoid synthesis error.
rtl/rx_phy/gxb_rx.qsys

RX Native PHY instance variant file.

rtl/rx_phy/gxb_rx_reset.qsys

RX Native PHY's transceiver PHY reset controller instance variant file.

rtl/tx_phy/gxb_tx.qsys

TX Native PHY instance variant file.
rtl/tx_phy/gxb_tx_reset.qsys

TX Native PHY's transceiver PHY reset controller instance variant file.

rtl/tx_phy/gxb_tx_fpll.qsys

TX Native PHY's FPLL instance variant file.

rtl/i2c_gpio_buf.qsys

I2C buffer instance variant file. This buffer is not used in this reference design.

rtl/video_pll_a10.qsys

IO PLL instance variant file.
rtl/example.sdc

Top level SDC timing constraint file.
script/build_sw.sh

Shell script to re-build the NIOS II software.

script/rerun.sh

Shell script to load the FPGA hardware image (.sof) and software image (.elf).

dp_core.sopcinfo

The build_sw.sh script uses this file to rebuild the Nios II software for the control Qsys system.

Others sopcinfo files

These files are not needed to rebuild the Nios II software.

quartus/dp_vip_xcvr.stp SignalTap II file for debug purpose.
rtl/a10_reconfig_arbiter.sv

HDL module to arbitrate access to the Avalon-MM interface of the TX and RX Native PHY. This module is needed for merging simplex TX/RX Native PHY into the same physical transceiver channel.

rtl/mr_rate_detect.v

HDL module to measure clock frequency.
rtl/a10_dp_demo.v

Top-level HDL file for this reference design.

rtl/bitec_reconfig_alt_a10.v

HDL module to dynamically reconfigure the TX/RX Native PHY and TX fPLL for data rate switching.

filelist.txt A list of all the files consisting in this design.
Level Two Title